Design Verification Engineer job opportunity at Altera Corporation.

Home Jobs In China Tag: Job Design Verification Engineer position at Altera Corporation


DatePosted 3 Days Ago bot
Altera Corporation Design Verification Engineer
Experience: 5-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Shanghai, China, China
loacation Shanghai, Chin..........China

Job Details: Job Description: Performs functional logic verification at multiple levels ( block, subsystem and full chip ) Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.  Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.  Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with Architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.  Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.  Maintains and improves existing functional verification infrastructure and methodology.  Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products Qualifications: BS, MS or PhD in Electrical or Computer Science Engineering or related field with 3-5+ years of technical experience. Validation/Verification. Related technical experience should be in/with: Pre Silicon OVM/UVM, System Verilog, constrained random verification methodologies. Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Scripting experience with TCL/PERL/Python etc., Formal verification experience, Experience in either Ethernet / PCIe / MACSEC / IPSEC protocols & FPGA architecture or FPGA prototyping Job Type: Regular Shift: Shift 1 (China) Primary Location: Shanghai, China Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Other Ai Matches

Graduate Talent - Applications Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Oracle Fusion Business Analyst - Invoice to Pay Applicants are expected to have a solid experience in handling Job related tasks
Power BI Developer Applicants are expected to have a solid experience in handling Job related tasks
Physical Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Design Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
FPGA Silicon Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior FPGA Security Architect– Aerospace, Defense & Government Applicants are expected to have a solid experience in handling Defense & Government related tasks
Principal NoC IP Micro-Architect Applicants are expected to have a solid experience in handling Job related tasks
Performance Power Validation Manager Applicants are expected to have a solid experience in handling Job related tasks
FPGA Development Tools Engineer Applicants are expected to have a solid experience in handling Job related tasks
Analog Circuit Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
FPGA IP Software Development Engineer Applicants are expected to have a solid experience in handling Job related tasks
Principal FPGA Compiler Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Sr. Fabric Data Engineer Applicants are expected to have a solid experience in handling Job related tasks
Sr. SoC Design Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
remote-jobserver Remote
Workday Solution Architect-Contract Applicants are expected to have a solid experience in handling Job related tasks
FPGA Firmware User Experience Validation Lead Applicants are expected to have a solid experience in handling Job related tasks
Oracle Fusion ERP OTC Architect Applicants are expected to have a solid experience in handling Job related tasks
Design Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Custom Physical Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Principal FPGA Compiler Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Machine Learning Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff FPGA Compiler Software Engineer Applicants are expected to have a solid experience in handling Job related tasks