Analog Circuit Design Engineer job opportunity at Altera Corporation.

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DatePosted 14 Days Ago bot
Altera Corporation Analog Circuit Design Engineer
Experience: 4-years
Pattern: full-time
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loacation San Jose, California, United States, United States Of America
loacation San Jose, Cali..........United States Of America

Job Details: Job Description: About Altera For decades, Altera has been a leader in programmable logic solutions, enabling customers across aerospace, automotive, data center, communications, and industrial markets to deliver innovative, high-performance systems. As part of our continued growth, we are expanding our mixed-signal and analog design capabilities to support next-generation FPGA and SoC platforms. About the Role As a Mixed Signal Design Engineer you will be part of a team designing various mixed-signal circuit designs on Altera FPGAs such as voltage regulators, bandgaps and bias circuits, Analog to digital converter (ADC), Delay locked loops (DLLs), high speed clock distribution  and other clocking circuits,  IO circuits such as high voltage IO, RCOMP/SCOMP, memory circuits etc. on advanced processes nodes and have an opportunity to work on a diverse set of blocks and tasks in all phases of the design. The ideal candidate will be  an independent self-starter who can own/design a custom analog or digital IP. An important part of this role is delivering all aspects of the design and collateral, including timing and reliability collateral. In addition, you should be able to drive transitions to AI tool-based design. You should be a motivated team-player who is able to work with cross-functional and cross-geo teams to understand, articulate and solve problems . Responsibilities Design, develop and deliver circuit building block schematic, perform pre layout and post layout design optimization to meet design specification across PVT, process variation sensitivity analysis, aging, EOS, RV checks for design reliability. Work with custom layout team to define plan (floorplan, routing, matching, metal grid etc) to meet circuit performance Collateral generation like circuit integration spec, and be a key driver to drive transition to AI tool-based design BMOD, timing model, power model, ICCT, IBIS, alpha numbers. Own specifications and design verification plans covering functionality, performance and reliability meeting high volume productization requirement. Collaborate with logic designer, logic verification designer, structural physical design engineers, integration engineers, signal integrity and power deliver engineer to define clear collateral handoff requirements to ensure efficient IP integration. Perform post silicon data analysis and debug and make necessary design enhancement to meet design specification. Conduct design reviews; actively contribute to design reviews Represent the team on related IP in cross-functional meetings and co-ordination of deliverables Work with external IP vendors as point of contact for analog designs Salary Range     The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.   $127,400 - $180,400 USD  We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.  Qualifications: Minimum Qualifications BSEE/MSEE/PhD in Electrical Engineering or equivalent with a minimum of 4+ years of experience in analog/mixed signal, high speed, or high voltage IO designs Direct design experience with analog and mixed signal circuits like amplifiers, comparators, regulators, IO, PLL etc Exposure to analog/mixed signal circuit design and layout flow and running post-layout simulations Solid understanding of analog design trade-offs and design for process variation and reliability in modern CMOS technologies Proficient in circuit design tools like Virtuoso, Spice, StarRC, Totem etc Understanding of Verilog, static timing analysis, UPF and related aspects of mixed signal design Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Austin, Texas, United States, Oregon Hillsboro Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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