Senior Staff FPGA Compiler Software Engineer job opportunity at Altera Corporation.

Home Jobs In Canada Tag: Job Senior Staff FPGA Compiler Software Engineer position at Altera Corporation


DatePosted 25 Days Ago bot
Altera Corporation Senior Staff FPGA Compiler Software Engineer
Experience: 15-years
Pattern: full-time
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loacation Toronto, Ontario, Canada, Canada
loacation Toronto, Ontar..........Canada

Job Details: Job Description: Become a member of our world-class software research and development team!  Altera® develops innovative programmable logic technologies that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities.  Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation for many customers worldwide. You will be architecting and developing leading-edge software innovations for Quartus, the tool that optimizes our FPGA devices, within a research-oriented team. Quartus is used by all FPGA acceleration technologies (including High Level Synthesis, FPGA AI Suite, DSP Builder, etc.). The Quartus Router and Retimer optimization engines are key to unlocking high performance, area and power efficiency for our customer's design applications. As part of the Quartus Router and Retimer team, your role will include: Leading research & development efforts to explore novel optimization algorithms for our FPGA CAD software tools, including global and detailed routing as well as state of the art retiming for our Hyperflex routing architecture Developing and optimizing the software to drive performance improvements by leveraging innovative FPGA hardware features Owning various modules of the Routing and Retiming engine from device modeling to timing closure to runtime Ideal candidates exhibit the following behavioral traits: Intellectual curiosity and a passion for exploring new technology Excellent problem-solving, debugging, and attention to detail Great communication, teamwork, and interpersonal skills Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success. ​     Estimated Salary Range: $ 139.0k – $201.2k CAD ​   ​   We use artificial intelligence to screen, assess, or select applicants for the position. ​ This posting is for an existing vacancy. ​ Canadian work experience is not required for this role.   Qualifications: Minimum Requirements: Degree in Electrical Engineering, Computer Engineering, Computer Science or related field MS + 15 years of industry software experience, or PhD + 10 years of industry software experience Desired/Preferred Skills: Significant experience coding & hands-on development of high performance multi-core software systems Extensive experience as an architect/technical lead for developing EDA/CAD routing algorithms for FPGAs Proven leadership skills for collaborative cross functional projects Experience with Altera® Quartus or AMD Vivado software Experience with graph theory and network based optimizations including pathfinding and combinatorial optimizations Experience with applying machine learning techniques to EDA software Job Type: Regular Shift: Shift 1 (Canada) Primary Location: Toronto, Ontario, Canada Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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