FPGA Circuit Design Engineer job opportunity at Altera Corporation.



DatePosted 30+ Days Ago bot
Altera Corporation FPGA Circuit Design Engineer
Experience: 12-years
Pattern: full-time
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation San Jose, California, United States, United States Of America
loacation San Jose, Cali..........United States Of America

Job Details: Job Description: Join Altera as a FPGA Circuit Design Engineer! The FPGA Circuit Design Engineer designs and develops FPGA circuits and IPs including FPGA core fabric logic, interconnect routing, clocking, configuration, configurable memory blocks, and network on chip. Other responsibilities include but are not limited to: Micro-architects and performs circuit and logic design, schematic entry, simulation, reliability verification, and verifies functionality to optimize FPGA circuits for power, performance, area, timing, and yield goals. Develops models and collaterals for FPGA circuits and IPs to integrate into FPGA hardware and software deliverables including circuit integration specifications, behavioral models, electrical rule checkers, design intent, and timing and power models. Works with microarchitecture, SoC/full chip, IP fabrics and interconnects, RTL design, and verification teams to develop new capabilities around FPGA solutions, design improved programmable logic designs, and deliver faster integration of FPGAs into larger systems. Salary Range     The pay range below is for Bay Area California only. Actual salary may vary based on   a number of   factors including job location, job-related knowledge, skills,   experiences ,   trainings , etc. We also offer incentive opportunities that reward employees based on individual and company performance.    $200.4 K   - $290.1 K   USD     We use artificial intelligence to screen, assess, or select applicants for the position.   Qualifications: Minimum Qualifications The candidate must have a Bachelor's or Master's Degree in Electronic Engineering or a related field, with 12+ years of FPGA design experience. Strong communication and documentation skills. Comfortable working in a dynamic environment that requires a broad range of technical expertise, including logic design, memory design, custom circuit design, SPICE and RV simulations, sign-off reviews, and oversight of physical design activities. Solid understanding of hardware VLSI design and advanced process technologies. Proficiency in programming languages such as Python, Perl, CSH, TCL, and Makefiles is a plus. Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Other Ai Matches

RTL Design Lead Hardware Engineer Applicants are expected to have a solid experience in handling Job related tasks
Principal FPGA Compiler Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
FPGA Circuit Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff FPGA Compiler Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Analog Layout Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior SOC Physical Design/Power Analysis/RDL Engineer Applicants are expected to have a solid experience in handling Job related tasks
Silicon Validation and Tool Development Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Hardware/Software ML Inference IP and Compiler Developer Applicants are expected to have a solid experience in handling Job related tasks
Senior FPGA Compiler Software Engineer Applicants are expected to have a solid experience in handling Job related tasks
Business Development Manager Applicants are expected to have a solid experience in handling Job related tasks
Logic Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Oracle EPM Architect / Application Engineer Applicants are expected to have a solid experience in handling Job related tasks
Lead Design Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Director of AI Transformation & Engineering Excellence Applicants are expected to have a solid experience in handling Job related tasks
Quartus Strategic Planner Applicants are expected to have a solid experience in handling Job related tasks
Senior Physical Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Exempt Tech Contract Employee Applicants are expected to have a solid experience in handling Job related tasks
Graduate Talent - Applications Engineer Applicants are expected to have a solid experience in handling Job related tasks
Firmware Development Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior DFT Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Cloud Systems and Solutions Engineer Applicants are expected to have a solid experience in handling Job related tasks
FPGA Circuit Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Physical Design Graduate Intern Applicants are expected to have a solid experience in handling Job related tasks