Functional Safety Architect job opportunity at Altera Corporation.

Home Jobs In India Tag: Job Functional Safety Architect position at Altera Corporation


DateMore Than 30 Days Ago bot
Altera Corporation Functional Safety Architect
Experience: 8-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Bengaluru, Karnataka, India, India
loacation Bengaluru, Kar..........India

Job Details: Job Description: Altera is a global leader in programmable logic and semiconductor solutions. We design cutting-edge technologies that enable innovation across AI, networking, data centers, and embedded applications. Our team is passionate about pushing the boundaries of what’s possible in silicon design.   Become a member of our world-class S o C architecture and development team!    Position Overview   We are seeking a highly motivated & passionate for safety, Functional Safety Architect to join our semiconductor architecture design team. In this role, you will own the device safety architecture and lead the efforts to achieve safety goals by developing technical safety concepts including safety mechanism s derived from safety analyses ; and allocating decomposed safety requirements to each IP sub-blocks for next-generation semiconductor devices .    You will collaborate with architects, IP owners, RTL design engineers , physical design , firmware and verification teams to deliver critical safety collaterals ensuring end goal of achieving successful functional safety certification .   Key Responsibilities   Collaborate with the Architects, Silicon Design, Software teams to architect new safety concepts and safety mechanism features and guide future development.   Perform safety analyses (FTA, FMEA, DFA methodologies) against CCF, CF to ensure FFI, independence & Fault tolerance requirements are met.   Define safe architecture patterns (lockstep CPUs, ECC memories, watchdogs, redundancy).   R eview and contribute to writing safety requirement specifications with FSEs.   Guide teams on ASIL /SIL decomposition, fault tolerance, diagnostics coverage, etc.   Review hardware/software safety designs for compliance and feasibility.   Collaborate with design verification teams to d efine safety V&V strategy (fault injection, fault simulation , test methodologies ).   Ensure achievement of diagnostic coverage metrics (SPFM, LFM, PMHF).   Qualifications: Minimum Requirements Bachelor’s or Master’s Degree in Electrical Engineering or equivalent   BS + 10 Years of silicon industry experience or MS + 8 years of silicon industry experience   Relevant safety professional certifications ( Eg. FSCP, FS Professional license)   Experience in certifying devices from concept through certification for ASICs/PLDs/CPUs with EXIDA, TUeV or Equivalent   Skilled with SysML , FMEA/FMEDA, FTA, HAZOP and requirements-management tooling (e.g., Jama).   Demonstrated strong ability to move seamlessly between levels of abstraction – from system to the “nuts and bolts” implementation   Excellent written & oral communication skills to construct clear, evidence-based safety arguments and build trust in safety cases with both internal and external stakeholders     Preferred Qualifications:   Familiarity with RTL coding and simulations/debug of S o C Architectures .   Desire to develop deep understanding of end user needs and engagement with customers to enable use of SoCs in safety design applications   Desire to commit and follow through on complex, multi-year programs   Ability to resolve complex issues in creative, efficient, and effective ways     Be self-driven and result oriented   Desire to work in a fast-paced environment   Job Type: Regular Shift: Shift 1 (India) Primary Location: Bengaluru, Karnataka, India Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Other Ai Matches

FPGA Circuit Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Lead Design Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Product Development Engineering Applicants are expected to have a solid experience in handling Job related tasks
Senior Static Timing Analysis (STA) Developer Applicants are expected to have a solid experience in handling Job related tasks
Firmware Developer Applicants are expected to have a solid experience in handling Job related tasks
Senior Design Automation Engineer - Front End Design Verification Applicants are expected to have a solid experience in handling Job related tasks
Analog Layout Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Product Marketing Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior FPGA Security Architect– Aerospace, Defense & Government Applicants are expected to have a solid experience in handling Defense & Government related tasks
Design Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Quartus Strategic Planner Applicants are expected to have a solid experience in handling Job related tasks
Functional Safety Architect Applicants are expected to have a solid experience in handling Job related tasks
Analog Layout Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
FPGA Development Tools Engineer Applicants are expected to have a solid experience in handling Job related tasks
FPGA Circuit Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
IP verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Firmware Functional Safety Engineer Applicants are expected to have a solid experience in handling Job related tasks
Product Development Engineer Applicants are expected to have a solid experience in handling Job related tasks
Transceiver & Protocol Applications Engineer Applicants are expected to have a solid experience in handling Job related tasks
Executive Administrative Assistant Applicants are expected to have a solid experience in handling Job related tasks
Principal NoC IP Micro-Architect Applicants are expected to have a solid experience in handling Job related tasks
Senior Manager - Network Security Applicants are expected to have a solid experience in handling Job related tasks
RTL Design Lead Hardware Engineer Applicants are expected to have a solid experience in handling Job related tasks