Principal Hardware Engineer - Board‑level system design - infrastructure/storage/network/PCIe Gen 5+/DDR4/5/Ethernet job opportunity at Marvell Technology, Inc..

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Marvell Technology, Inc. Principal Hardware Engineer - Board‑level system design - infrastructure/storage/network/PCIe Gen 5+/DDR4/5/Ethernet
Experience: 10-years
Pattern: full-time
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loacation Irvine, CA, United States Of America
loacation Irvine, CA....United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact The Hardware Design Senior Staff Engineer will serve as a key member of the Hardware Design team within the Operations PE/TE organization. This role is responsible for developing board level hardware solutions from early prototype through high volume production. The engineer will collaborate with multiple advanced technology groups, supporting products and platforms across Fibre Channel (FC) networking and storage, network security processors featuring custom ARM based architectures, and custom ASIC solutions built on 3nm technologies with high speed SerDes for large scale data center applications. What You Can Expect Seeking a versatile, self-motivated, team-oriented board design engineer to develop high density, high volume next generation products. Our products support a wide range of communication‑infrastructure applications, including Fiber Channel (FC), NICs, optical modules, network security, data‑center systems, and cloud‑computing platforms. The candidate will collaborate closely with Marvell ASIC/hardware/software design teams, lead technical discussions with customers, and oversee design deliverables from Contract Manufacturers to ensure high‑quality execution. The candidate will also have a good debug skills and experience in using lab equipment. Expertise in design for optimum signal and power integrity as well as hands-on lab measurements experience is a must. Provide technical and engineering support to strategic customers, including creation and presentation of power point files for customer review and discussions Work directly with customers to address design challenges, debug failures, and ensure successful product integration. Design high‑performance board‑level systems for storage, network security, and custom ASIC applications. Manage designs with JDM partners to provide design guidance, support build readiness and ensure production quality. Define, design, and review schematics from internal hardware teams and JDM, with emphasis on high‑speed signal integrity, power integrity, and cost‑optimized designs for high‑volume production. Review PCB layouts in collaboration with layout engineering teams. Work closely with the internal board development, DVT and SI teams to make sure board  issues are addressed, resolved, and closed Conduct design reviews with clear documentation, and provide technical leadership throughout the product development cycle. Collaborate with cross‑functional teams to ensure product performance, reliability, and quality. Define, document, execute, and report on board‑level electrical tests. Facilitate technical discussions and drive resolution of complex engineering issues. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 10+ years of relevant industry experience, OR a Master’s degree with 10+ years of experience. 10+ years of experience in board‑level hardware design and system architecture, including fine pitch components and micro-vias. 5+ years of experience working with ODM/JDM Proficiency with schematic capture tools (Cadence OrCAD, Allegro HDL) and familiarity with Allegro PCB layout tools. Strong expertise in high‑speed interfaces and protocols, including PCIe Gen5+, DDR4/5, Ethernet, QSPI, and USB etc. Demonstrated customer‑facing experience with excellent verbal and written communication skills. Proven critical‑thinking abilities, strong problem‑solving skills, and a sense of ownership for team and project outcomes. Advanced lab skills with hands‑on experience in hardware bring‑up, system‑level testing, power supply design, and troubleshooting. Experience working with PCIe, Ethernet, and OCP standards. Knowledge of high‑speed SerDes technologies, including 112G/224G. Familiarity with EMC/EMI compliance, regulatory and safety standards, and the ability to interpret test lab reports. Basic Linux proficiency for system test environment setup (highly preferred). Working knowledge of mechanical and thermal design principles, including interpretation of 2D and 3D drawings. Experience with Agile PLM tools is considered a plus. Expected Base Pay Range (USD) 152,300 - 225,440, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-AP1

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