Design Verification Engineer, Senior Principal job opportunity at Marvell Technology, Inc..

Home Jobs In United States Of America Tag: Senior Principal Design Verification Engineer, Senior Principal position at Marvell Technology, Inc.


DatePosted 10 Days Ago bot
Marvell Technology, Inc. Design Verification Engineer, Senior Principal
Experience: 10-years
Pattern: full-time
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Senior Principal

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loacation Santa Clara, CA, United States Of America
loacation Santa Clara, C..........United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers' specifications whether they're a major telecom organization or automotive company, etc. What You Can Expect Job Responsibilities 1. Technical Authority & Stewardship Serve as the final technical authority for the most complex design and verification decisions. Define and uphold verification architecture, standards, and best practices across multiple programs. 2. Organization‑Level Impact Influence verification methodology and tooling beyond a single project or SoC. Drive reuse, scalability, and consistency across teams and product lines. 3. Strategic & Long‑Term Thinking Anticipate future technical challenges and shape the DV technology roadmap. Balance short‑term execution with long‑term architectural health. 4. Cross‑Functional Leadership Align design, architecture, firmware, and verification teams. Act as a trusted technical arbitrator when tradeoffs or conflicts arise. 5. Risk Ownership & Executive Communication Identify systemic technical risks early and define mitigation strategies. Communicate risks, tradeoffs, and recommendations clearly to senior leadership. 6. Mentorship & Bar Raising Mentor senior engineers and principals; develop future technical leaders. Set the technical and behavioral bar for engineering excellence. 7. Talent & Culture Influence Influence hiring decisions, role definitions, and leveling expectations. Reinforce a culture of rigor, openness, and continuous learning. As a leading member of the Network Switching team you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development.  Your role may also include project management and leading a team of verification engineers on a project level. Activities may include: Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete. Developing tests and tuning the environment to achieve coverage goals. Debugging failures and working with designers to resolve issues. Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs. Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment. Unit and regression testing of software tools. What We're Looking For Requirements BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience). Proven track records of leading Design Verification implementation activity. Tape-out of complex SOC under tight schedule. In depth understanding and experience with System Verilog, UVM. In depth experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment. Experience with scripting language such as Python or Perl and EDA Verification tools. Experience with Object-Oriented Design and implementation. Good understanding of Linux O.S. Good programming skills desired, especially C++ and ARM assembly. Understanding of networking protocols, a plus. Other Skills Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision. Requires the ability to accept and work with differing opinions. Cannot be a close-minded developer. Must be able to learn on the fly and work in a fast-paced environment. Expected Base Pay Range (USD) 182,360 - 273,200, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-JT2

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