Senior Staff Engineer, Digital IC Design job opportunity at Marvell Technology, Inc..

Home Jobs In Vietnam Tag: Digital IC Design Senior Staff Engineer, Digital IC Design position at Marvell Technology, Inc.


DatePosted 14 Days Ago bot
Marvell Technology, Inc. Senior Staff Engineer, Digital IC Design
Experience: 5-years
Pattern: full-time
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Digital IC Design

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loacation Ho Chi Minh, Vietnam
loacation Ho Chi Minh....Vietnam

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Connectivity BU develops industry leading PAM4 optical digital signal processors (DSPs) power the optical interconnects inside the world’s cloud and AI data centers, and support both Ethernet and InfiniBand architectures. With increasing demands for training, inference and cloud computing, operators must quickly scale out their networks with reliable, low-latency, high-bandwidth connectivity. Marvell PAM4 DSPs deliver the performance and versatility needed to support AI and cloud frontend and backend networks at 1.6T, 800G, 400G, 200G and 100G What You Can Expect What You Can Expect As ASIC design engineer you will be responsible for the design, verification, and evaluation of digital circuits in high-speed data communication ICs. Develop ASIC specification and micro-architecture of signal processing and communications algorithms. Analyze DSP challenges and opportunities, explore and compare different optimization directions, and generate trade-off curves for performance and cost (complexity/power/area/design time) Work on high-efficiency DSP design Design RTL for various PHY transceivers with data rates from 25Gbps to 224Gbps for diverse applications. Collaborate with Analog, Digital Verification, Firmware, and Application Engineering teams to deliver competitive PHY transceiver solutions across all product lines. Participate in various aspects of chip design RTL development, functional verification, RTL lint, cross clock domain (CDC) analysis, synthesis, formal equivalence, static timing analysis and PPA analysis. Post-silicon debug and correlation   What We're Looking For What We're Looking For Strong experience in high speed DSP/FEC (Forward Error Correction)  Hands on experience with matching DSP block model functionality to RTL's, synthesis, static timing analysis and functional verification  Strong system level modeling, debugging and troubleshooting Strong language user in Matlab, Verilog, System Verilog, Perl, Unix Shell.  Experience of entire design cycle from micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment.  Experience in both RTL development (block and subsystem level) and gate level verification and debug.  Understanding of Design-for-Test (DFT) concepts, including Scan and BIST  Experience with chip bring up and functional validation of the product in the lab  Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment  Strong communication skills and effective team collaboration abilities  Bachelor’s degree in Computer Engineering, Electrical Engineering, or related fields with 5+ years of relevant experience, or a Master’s/PhD with 2+ years of relevant experience.   Additional Compensation and Benefit Elements Competitive salary, plus 13th-month salary and performance-based bonus RSUs (Restricted Stock Units) for new joiners and on-going annually Premium health & accident insurance for you and your family (spouse and children) Annual medical check-up at a designated hospital arranged by Marvell Generous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidays Exciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-UN1

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