Architecture Validation (L2, L3, C/C++, Python automation, Device modeling) job opportunity at Marvell Technology, Inc..

Home Jobs In India Tag: L3, C/C++, Python automation, Device modeling) Architecture Validation (L2, L3, C/C++, Python automation, Device modeling) position at Marvell Technology, Inc.


DatePosted 18 Days Ago bot
Marvell Technology, Inc. Architecture Validation (L2, L3, C/C++, Python automation, Device modeling)
Experience: 20-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

L3, C/C++, Python automation, Device modeling)

Copy Link Report
degreeOND
loacation Bangalore, India
loacation Bangalore....India

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact The Teralynx switch architecture team is responsible for the architecture of Marvell’s cutting-edge data center switch ASICs. This includes defining the Product Architecture, Architectural Modeling, Performance Modeling and Architecture Validation among other tasks. What You Can Expect As part of the Teralynx Switch Architecture team, you will help shape our next generation switch ASICs from concept through development to production.   Detailed Architectural Validation and Behavioral modeling What We're Looking For Bachelor’s/ Master's degree in  Computer Science,  Electrical Engineering or related fields with 7 to 20 years of related  professional experience. Deep knowledge and experience with Layer 2 / Layer 3 forwarding, QoS and networking protocols Experience with micro-architecture, verification and execution of networking silicon chips and sub-systems. In depth knowledge of C / C++ and Python Strong conceptual thinking, problem solving and communication skills Ability to effectively collaborate across multiple teams and across geographies Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-RS1

Other Ai Matches

Software Engineer Intern Applicants are expected to have a solid experience in handling Job related tasks
Senior Director Product Security Applicants are expected to have a solid experience in handling Job related tasks
Director of Product Marketing Applicants are expected to have a solid experience in handling Job related tasks
Technical Lead, IC Design Applicants are expected to have a solid experience in handling IC Design related tasks
Senior Staff RTL Design /Verification Applicants are expected to have a solid experience in handling Job related tasks
Senior Principal Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Senior Staff Product Engineering Applicants are expected to have a solid experience in handling Job related tasks
RTL IP Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Principal Application Engineer – SoC Embedded Systems (validation, characterization, and customer deployment support) Applicants are expected to have a solid experience in handling characterization, and customer deployment support) related tasks
Analog IC Design Intern (Optical PHY) Applicants are expected to have a solid experience in handling Job related tasks
Architecture - Architecture ASIC / System Applicants are expected to have a solid experience in handling Job related tasks
Principal Test Engineer Applicants are expected to have a solid experience in handling Job related tasks
Advanced Packaging SI/PI Senior Engineer Applicants are expected to have a solid experience in handling Job related tasks
Product Engineer Applicants are expected to have a solid experience in handling Job related tasks
Physical Design Senior Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
DSP Architect Applicants are expected to have a solid experience in handling Job related tasks
Staff Analog Layout Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Design, Mixed-Signal Design Applicants are expected to have a solid experience in handling Mixed-Signal Design related tasks
Firmware Engineer -PCIe post silicon bring up, function validations, protocol Applicants are expected to have a solid experience in handling function validations, protocol related tasks
Advanced Packaging SI/PI Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Staff Engineer, Application Engineering Applicants are expected to have a solid experience in handling Application Engineering related tasks
Principal Hardware Design Engineer - PCB Board Level Circuit Design Simulation Test Applicants are expected to have a solid experience in handling Job related tasks