Senior Staff Engineer, Static Timing Analysis (STA) Engineer job opportunity at Marvell Technology, Inc..

Home Jobs In United States Of America Tag: Static Timing Analysis (STA) Engineer Senior Staff Engineer, Static Timing Analysis (STA) Engineer position at Marvell Technology, Inc.


DatePosted 26 Days Ago bot
Marvell Technology, Inc. Senior Staff Engineer, Static Timing Analysis (STA) Engineer
Experience: 8-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Static Timing Analysis (STA) Engineer

Copy Link Report
degreeOND
loacation Santa Clara, CA, United States Of America
loacation Santa Clara, C..........United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact The Design Center Engineering Physical Design team at Marvell in Santa Clara is seeking a Senior Staff Engineer, Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projects—from artificial intelligence and machine learning to advanced wired and wireless infrastructure—using the latest technology nodes.Our team leverages cutting-edge EDA tools to solve complex challenges and ensure our designs meet critical performance, power, and area (PPA) goals. This role involves close collaboration with Physical Design, Design for Test (DFT), and other cross-functional teams across both local and global sites. What You Can Expect This role is based in Santa Clara, CA. Relocation will be required if you are not already in the area. You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. Perform timing analysis and closure on complex partitions Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner Implement/support multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools Work with RTL design teams to drive assembly and design closure Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation What We're Looking For If you're looking to apply your STA expertise in a dynamic and forward-thinking environment, this is a great opportunity to explore. Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field. 8+ years experience in back-end physical design and verification. Familiar with hierarchical physical design strategies, methodologies and deep sub-micron technology issues like N5/N3/N2. Familiar with ASIC design flow, Verilog HDL, synthesis and timing closure. Expertise in full-chip & sub-hierarchy integration preferred Experience integrating and taping out large designs utilizing a digital design environment Good understanding of RTL to GDS flows and methodology Good scripting skills in Perl, tcl and Python Strong knowledge in static timing analysis (Primetime preferred) and SDC timing constraints Understanding of digital logic and computer architecture Knowledge of Verilog Good communication skills and self-discipline contributing in a team environment Experience with multi-voltage and low-power design techniques is a plus Experience with Cadence Innovus is preferred Expected Base Pay Range (USD) 131,010 - 196,300, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-VM1

Other Ai Matches

Senior Staff Engineer, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Sr. Principal Engineer, Advanced Packaging Applicants are expected to have a solid experience in handling Advanced Packaging related tasks
Manager of Procurement - semiconductor manufacturing/OSAT Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Analog Mixed-Signal Design - Optical Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Digital Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Firmware Engineer -PCIe post silicon bring up, function validations, protocol Applicants are expected to have a solid experience in handling function validations, protocol related tasks
Senior Principal Engineer - Networking/Switching Silicon Semiconductor AI Infrastructure Embedded Firmware Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Global Mobility & Immigration Specialist Applicants are expected to have a solid experience in handling Job related tasks
Technical Director, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Senior Director Product Security Applicants are expected to have a solid experience in handling Job related tasks
Senior Director Product Line Management - CPO Applicants are expected to have a solid experience in handling Job related tasks
Digital Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Advanced Packaging Engineer - SI/PI Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Engineer, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Staff to Senior Staff Engineer, DFT Applicants are expected to have a solid experience in handling DFT related tasks
AI Developer Platforms (Security) Applicants are expected to have a solid experience in handling Job related tasks
Design Verification Engineer, Principal Applicants are expected to have a solid experience in handling Principal related tasks
Memory Layout Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Physical Verification CAD engineer Applicants are expected to have a solid experience in handling Job related tasks
Director Hardware Application Engineering Applicants are expected to have a solid experience in handling Job related tasks
Staff Firmware Engineer - high-speed interconnects /custom silicon/ASIC design / microcontroller architectures / Applicants are expected to have a solid experience in handling Job related tasks
Analog IC Design, Staff Engineer Applicants are expected to have a solid experience in handling Staff Engineer related tasks
Distinguished Engineer, Verification Applicants are expected to have a solid experience in handling Verification related tasks