Staff Engineer, Analog Layout job opportunity at Marvell Technology, Inc..

Home Jobs In Singapore Tag: Analog Layout Staff Engineer, Analog Layout position at Marvell Technology, Inc.


DateMore Than 30 Days Ago bot
Marvell Technology, Inc. Staff Engineer, Analog Layout
Experience: 8-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Analog Layout

Copy Link Report
degreeOND
loacation Singapore, Singapore
loacation Singapore....Singapore

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As an Analog Layout Staff Engineer with Marvell, you’ll contribute to the development of High-Speed SerDes, Broadband Analog and Computing/Storage-Memory Data-Transport products (including functional blocks such as high-speed analog/digital, multi-GHz ADC/DAC, PLL/DLL serial and parallel I/O, and clock generation/distribution for custom ICs). What You Can Expect Working with global teams across Argentina, Singapore, the U.S., and Europe, you will run simulations and verifications using Cadence Virtuoso, collaborating closely with the designer to refine and debug iteratively until the design meets specifications. Project durations vary from a few months to a year and a half with flexibility to switch based on changing priorities is appreciated Regular meetings with your paired designer ensure collaborative information sharing, integral to Marvell's commitment to partnership and teamwork. Key contributor and crucial role in the project lifecycle, participating in routine meetings as a technical mentor, layout team, and the broader project team. Provide updates on progress and may involve presenting specific issues or solutions encountered during the development of cutting-edge technologies Continuous learning and knowledge-sharing among colleagues What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and at least 8+ years of related professional experience or Master’s degree in Computer Science, Electrical Engineering or related fields with 5+ professional experience. Deep understanding of layout methodology from initial chip planning to tape-out and parasitic optimizing in layout Experience in advanced process technology and Fin-FET is preferred Have a high level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports Possess high-level proficiency/knowledge of Synopsys or CADENCE layout entry tools Programming skills in any of the following are a plus: Skill or Ample or Perl, etc. Strong technical and analytical background, problem solving skills, etc. The candidate must have a proven record of laying out high-performance analog circuits in state-of-the-art CMOS process technologies, successfully performed top-level integrations, and placed products into volume production multiple times. Proficient in spoken and written English Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-ST1

Other Ai Matches

Principal/Staff Engineer, DFT Engineering Applicants are expected to have a solid experience in handling DFT Engineering related tasks
SYN/STA Engineering Intern (Optical PHY) Applicants are expected to have a solid experience in handling Job related tasks
Principal Marketing Technology Solutions Lead Applicants are expected to have a solid experience in handling Job related tasks
DFT Principal Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Counsel (Vietnam Legal Lead) Applicants are expected to have a solid experience in handling Job related tasks
senior staff signal/power integrity engineer Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Engineer, Package Engineering Applicants are expected to have a solid experience in handling Package Engineering related tasks
Senior Staff Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Test Hardware Engineer Applicants are expected to have a solid experience in handling Job related tasks
Signal Integrity Engineer Intern (Cloud Platform Optics) - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Staff Engineer, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Director, Software Engineering (Networking, Switch, SONiC) Applicants are expected to have a solid experience in handling Software Engineering (Networking, Switch, SONiC) related tasks
Emulation Intern Applicants are expected to have a solid experience in handling Job related tasks
Principal Engineer, Design For Test Applicants are expected to have a solid experience in handling Design For Test related tasks
Staff Engineer, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Advanced Packaging Engineer - SI/PI Applicants are expected to have a solid experience in handling Job related tasks
Senior Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Test Engineer Applicants are expected to have a solid experience in handling Job related tasks
Package Development, Signal Integrity and Power Integrity Engineer, Senior Principal Applicants are expected to have a solid experience in handling Signal Integrity and Power Integrity Engineer, Senior Principal related tasks
Software Engineer (L1, L2, L3, C, Linux, DPDK, Switch) Applicants are expected to have a solid experience in handling L2, L3, C, Linux, DPDK, Switch) related tasks
Software/Firmware Engineer - RISC-V Architecture / PCIe: protocol, post silicon bring up, validation) Applicants are expected to have a solid experience in handling post silicon bring up, validation) related tasks