Sr. Principal Engineer, Advanced Packaging job opportunity at Marvell Technology, Inc..



DatePosted 30+ Days Ago bot
Marvell Technology, Inc. Sr. Principal Engineer, Advanced Packaging
Experience: 15-years
Pattern: full-time
apply Apply Now
Salary:
Status:

Advanced Packaging

Copy Link Report
degreeOND
loacation Austin, TX, United States Of America
loacation Austin, TX....United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact The Marvell Advanced Packaging team is responsible for package design and technology development to meet the electrical, mechanical, thermal and system requirements for the next generation high performance computing (HPC), Artificial Intelligence (AI) and networking solutions. The group focuses on signal integrity, power integrity, thermal integrity, mechanical integrity, high speed signaling and complex power delivery networks (PDNs) requiring innovative and custom solutions to meet constantly evolving customer needs. Many of the new designs require multi-chip, multiple component configurations involving, but not limited to, 2.5D and 3D packages, Co-packaged copper or optics and advanced substrates. Marvell has partnered with the world's leading manufacturers to solve our customer’s most challenging designs and integrations with industry-leading packaging technologies What You Can Expect Lead the development and optimization of advanced packaging solutions, including 2.5D/3D architectures (e.g., CoWoS, EMIB, CPO, CPC). Evaluate package and PCB designs to meet challenging electrical requirements. Collaborate closely with physical design and IP teams to optimize electrical performance. Execute SI/PI simulations and sign-off using industry-standard EDA tools. Define and drive strategic packaging initiatives aligned with Marvell’s technology roadmap. Lead design and development efforts for optoelectronic packaging, including integration of photonic components and co-design with electrical interconnects. Mentor engineers and foster a culture of innovation and knowledge sharing. Engage with cross-functional teams and external partners to influence design and manufacturing strategies. Manage package design and development programs involving global, cross-functional teams. What We're Looking For We are seeking a Senior Principal Engineer with deep expertise in advanced package technology, including signal integrity (SI), power integrity (PI), and high-performance packaging architectures. This role is ideal for a technical leader who thrives in complex design environments and is passionate about driving innovation in packaging and interconnect technologies. The ideal candidate will also have hands-on experience in the design and development of optoelectronic packaging, including integration of photonic components and high-speed electrical interfaces. This position offers significant opportunities for growth, including leading strategic packaging initiatives, mentoring engineering talent, and influencing Marvell’s technology roadmap. Leadership experience, either as a people manager or technical lead is a strong plus. Other Qualifications Bachelor’s degree in Electrical Engineering or related field with 15+ years of experience in package design, or Master’s/PhD with 10+/8+ years of relevant experience. Proven expertise in SI/PI fundamentals and simulation methodologies. Experience with EDA tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, PowerSI, SIwave. Familiarity with packaging technologies, substrate design rules, materials, and assembly processes. Strong understanding of circuit extraction and simulation workflows. Experience in optoelectronic packaging design and development, including photonic-electronic integration. Ability to perform routing feasibility studies using tools like Cadence APD or PCB Editor. Excellent communication, presentation, and documentation skills. Ability to work effectively across geographies and time zones. Expected Base Pay Range (USD) 0 - 0, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-MM1

Other Ai Matches

Senior Staff Engineer, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Sr. Principal Engineer, Advanced Packaging Applicants are expected to have a solid experience in handling Advanced Packaging related tasks
Manager of Procurement - semiconductor manufacturing/OSAT Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Analog Mixed-Signal Design - Optical Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Digital Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Firmware Engineer -PCIe post silicon bring up, function validations, protocol Applicants are expected to have a solid experience in handling function validations, protocol related tasks
Senior Principal Engineer - Networking/Switching Silicon Semiconductor AI Infrastructure Embedded Firmware Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Global Mobility & Immigration Specialist Applicants are expected to have a solid experience in handling Job related tasks
Technical Director, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Senior Director Product Security Applicants are expected to have a solid experience in handling Job related tasks
Senior Director Product Line Management - CPO Applicants are expected to have a solid experience in handling Job related tasks
Digital Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Advanced Packaging Engineer - SI/PI Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Engineer, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Staff to Senior Staff Engineer, DFT Applicants are expected to have a solid experience in handling DFT related tasks
AI Developer Platforms (Security) Applicants are expected to have a solid experience in handling Job related tasks
Design Verification Engineer, Principal Applicants are expected to have a solid experience in handling Principal related tasks
Memory Layout Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Physical Verification CAD engineer Applicants are expected to have a solid experience in handling Job related tasks
Director Hardware Application Engineering Applicants are expected to have a solid experience in handling Job related tasks
Staff Firmware Engineer - high-speed interconnects /custom silicon/ASIC design / microcontroller architectures / Applicants are expected to have a solid experience in handling Job related tasks
Analog IC Design, Staff Engineer Applicants are expected to have a solid experience in handling Staff Engineer related tasks
Distinguished Engineer, Verification Applicants are expected to have a solid experience in handling Verification related tasks