Digital Design Engineer job opportunity at Marvell Technology, Inc..

Home Jobs In Spain Tag: Job Digital Design Engineer position at Marvell Technology, Inc.


DatePosted 30+ Days Ago bot
Marvell Technology, Inc. Digital Design Engineer
Experience: 5-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Barcelona, Spain, Spain
loacation Barcelona, Spa..........Spain

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design infrastructure, methodology and workflows. What You Can Expect Develop and maintain leading-edge RTL validation flows, such as RTL linting/CDC or timing constraint validation,   addressing the needs of Marvell’s various Business Units. Keep up with process and tool evolutions, enable new technologies into design team execution flows. Leverage AI tools to enhance the efficiency and accuracy of CAD flows. Contribute to the deployment and support of these flows. Work in collaboration with the rest of the team to ensure optimal integration inside the overall CAD platform. Generate, collect, centralize and disseminate knowledge around RTL methodology. Interface with EDA vendors for optimal tool usage. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience. Good level in scripting in Tcl and Python in the context of flow development. Proficiency in Verilog / System Verilog Design and Verification. Experience in RTL linting tools, including clock domain crossing (CDC). Experience in git revision control. Knowledge in Equivalence Checking for both RTL to gates and gates to gates  in LEC or in Formality is highly desirable Demonstrate good analysis and problem-solving skills. Out-of-the-box thinking. Team player with good verbal and written communication skills. A keen eagerness to learn new skills is also important. Preferred Qualifications: Knowledge in writing, validating and debugging timing constraints (SDC) Experience writing code using AI assistants. High speed and low power implementation techniques/trade-offs. Knowledge in Synthesis tools, and downstream integration with P&R tools. Knowledge in UPF definition and multiple power domains implementation. Implementing Functional ECOs, ideally having setup ECO flows, either LEC eco or Formality ECO. Static Timing Analysis, setup and analyze STA results. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity   As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.   Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-AB1

Other Ai Matches

Staff Firmware Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Design, Mixed-Signal Design Applicants are expected to have a solid experience in handling Mixed-Signal Design related tasks
Senior Staff Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Principle FAE, ASIC Applicants are expected to have a solid experience in handling ASIC related tasks
Director of Product Marketing Applicants are expected to have a solid experience in handling Job related tasks
Principal Demand Planner Applicants are expected to have a solid experience in handling Job related tasks
Senior Principal Engineer, Reliability Applicants are expected to have a solid experience in handling Reliability related tasks
Staff DFT Engineer Applicants are expected to have a solid experience in handling Job related tasks
Staff Application Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Design Verification engineer Applicants are expected to have a solid experience in handling Job related tasks
Principal Analog Mixed-Signal IC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Director Customer Support - US Customer Solutions Group Applicants are expected to have a solid experience in handling Job related tasks
Design/DSP/Verification Intern - PhD Degree Applicants are expected to have a solid experience in handling Job related tasks
Staff Test Engineer (Optical Module) Applicants are expected to have a solid experience in handling Job related tasks
Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Physical Design Senior Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Director, Assistant General Counsel Applicants are expected to have a solid experience in handling Assistant General Counsel related tasks
Principal Technical Program Manager-IP conception/design to SoC/platform-level implementation and validation program execution Applicants are expected to have a solid experience in handling Job related tasks
Principal Engineer, Advanced Packaging Applicants are expected to have a solid experience in handling Advanced Packaging related tasks
Senior Staff Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Silicon Validation Engineer Applicants are expected to have a solid experience in handling Job related tasks
Design Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Advanced Packaging Pathfinding and Development - Signal and Power Integrity Sr Principal Engineer Applicants are expected to have a solid experience in handling Job related tasks