Principal Digital IC Design Engineer job opportunity at Marvell Technology, Inc..

Home Jobs In United States Of America Tag: Job Principal Digital IC Design Engineer position at Marvell Technology, Inc.


DatePosted 30+ Days Ago bot
Marvell Technology, Inc. Principal Digital IC Design Engineer
Experience: 15-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Santa Clara, CA, United States Of America
loacation Santa Clara, C..........United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a Principal Digital IC Design Engineer within Custom Silicon Engineering (CCS), you will be part of a high-performance RTL team responsible for architecting and implementing advanced SoC designs. CCS serves as the core execution engine for customer-driven silicon programs, delivering RTL, DV, and integration across compute, connectivity, and memory subsystems. You’ll collaborate with internal architecture, DV, and physical design teams, as well as external IP vendors and customer engineering teams. Your work will directly influence tapeout schedules, silicon bring-up, and product qualification. What You Can Expect Lead micro-architecture and RTL development for compute and connectivity subsystems, including memory controllers, PCIe/CXL interfaces, and D2D links. Drive HW/SW co-design and integration across multi-die SoC platforms. Collaborate with architects and DV engineers to ensure functional correctness, timing closure, and power optimization. Own RTL delivery milestones from ASR through PRQ, including support for emulation, silicon bring-up, and validation. Interface with external IP vendors and internal CAD teams to ensure IP integration and tool flow compatibility. What We're Looking For Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 10–15 years of experience, or Master’s/PhD with 5–10 years of experience in digital IC design. Deep understanding of SoC architecture, processor subsystems, memory controllers, and high-speed interfaces. Expertise in Verilog/VHDL, RTL linting (Spyglass), CDC analysis, and synthesis readiness. Proficiency in scripting languages (Python, Perl) for design automation. Proven success in delivering production-quality RTL under aggressive schedules. Experience with CXL, PCIe, DDR, and D2D protocols is highly desirable. Expected Base Pay Range (USD) 146,850 - 220,000, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity   As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.   Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SA1

Other Ai Matches

Staff Engineer, Application Engineering Applicants are expected to have a solid experience in handling Application Engineering related tasks
Principal Engineer, Design For Test Applicants are expected to have a solid experience in handling Design For Test related tasks
Advanced Packaging Technology Pathfinding and Development Engineer Applicants are expected to have a solid experience in handling Job related tasks
Silicon Photonics Validation Engineer Applicants are expected to have a solid experience in handling Job related tasks
Firmware Engineer -PCIe post silicon bring up, function validations, protocol Applicants are expected to have a solid experience in handling function validations, protocol related tasks
Senior Staff Engineer, Static Timing Analysis (STA) Engineer Applicants are expected to have a solid experience in handling Static Timing Analysis (STA) Engineer related tasks
Senior Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Hardware Validation Intern Applicants are expected to have a solid experience in handling Job related tasks
Principal Application Engineer – SoC Embedded Systems (validation, characterization, and customer deployment support) Applicants are expected to have a solid experience in handling characterization, and customer deployment support) related tasks
Senior Staff ASIC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Business Operations Analyst - Finance, Data Analytics, Costing and Pricing Applicants are expected to have a solid experience in handling Data Analytics, Costing and Pricing related tasks
Analog IC Design Intern - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Principal Customer Quality Engineer Applicants are expected to have a solid experience in handling Job related tasks
Principal/Staff Engineer, DFT Engineering Applicants are expected to have a solid experience in handling DFT Engineering related tasks
Senior Manager, Communications (Global Security) Applicants are expected to have a solid experience in handling Communications (Global Security) related tasks
System Design and Silicon Validation Intern (Connectivity) Applicants are expected to have a solid experience in handling Job related tasks
Director Product Marketing Enterprise Switching Applicants are expected to have a solid experience in handling Job related tasks
Hardware Validation Intern - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Physical Design Senior Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Analog IC Design Engineer Intern Applicants are expected to have a solid experience in handling Job related tasks
Senior Director Information Technology Applicants are expected to have a solid experience in handling Job related tasks
Principal Demand Planner Applicants are expected to have a solid experience in handling Job related tasks
Windows Device Driver Developer ( C, Kernel Programming, Storage protocols ) Applicants are expected to have a solid experience in handling Kernel Programming, Storage protocols ) related tasks