Physical Design Senior Staff Engineer job opportunity at Marvell Technology, Inc..



DatePosted 30+ Days Ago bot
Marvell Technology, Inc. Physical Design Senior Staff Engineer
Experience: 5-years
Pattern: full-time
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Yokneam, Israel
loacation Yokneam....Israel

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact The CCDS-Switching Physical Engineering Place & Route team involves significantly in developing Marvell products for the datacenter market. Starting from the early stages of floor planning through physical integration of Place, Route, Power, Physical Verification, Analog connectivity and Chip IO interface towards package and system, beside preparing Tapeout database for fabrication. What You Can Expect Designing for advanced process nodes (3nm and 2nm). The candidate will join a team of expert Layout engineers, developing Marvell Switches devices Layout till Tape-out. Our team is looking for an experienced Place & Route team member for implementing our advanced networking devices for datacenter market. As a member you will be challenged with complex physical integrations and verification. In addition, you will work collaboratively with expert interfaces such as: Design, Full-Chip timing, Signal integrity, Package and Circuit Design. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields. At least 5 years of experience in full-chip physical integration, manual and automatic layout (Place & Route) implementations. Rich familiarity with EDA Place & Route tools as Innovus or FC/ICC2. Ability to implement complex modules and Top hierarchies from Netlist to GDS, including all stages from Floorplan till Tape-out. Deep practical knowledge in physical verification for sign-off quality in advanced processes as 5nm and newer. TCL scripting capabilities. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity   As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.   Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SJ1

Other Ai Matches

Senior Staff Engineer, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Sr. Principal Engineer, Advanced Packaging Applicants are expected to have a solid experience in handling Advanced Packaging related tasks
Manager of Procurement - semiconductor manufacturing/OSAT Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Analog Mixed-Signal Design - Optical Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Digital Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Firmware Engineer -PCIe post silicon bring up, function validations, protocol Applicants are expected to have a solid experience in handling function validations, protocol related tasks
Senior Principal Engineer - Networking/Switching Silicon Semiconductor AI Infrastructure Embedded Firmware Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Global Mobility & Immigration Specialist Applicants are expected to have a solid experience in handling Job related tasks
Technical Director, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Senior Director Product Security Applicants are expected to have a solid experience in handling Job related tasks
Senior Director Product Line Management - CPO Applicants are expected to have a solid experience in handling Job related tasks
Digital Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Advanced Packaging Engineer - SI/PI Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Engineer, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Staff to Senior Staff Engineer, DFT Applicants are expected to have a solid experience in handling DFT related tasks
AI Developer Platforms (Security) Applicants are expected to have a solid experience in handling Job related tasks
Design Verification Engineer, Principal Applicants are expected to have a solid experience in handling Principal related tasks
Memory Layout Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Physical Verification CAD engineer Applicants are expected to have a solid experience in handling Job related tasks
Director Hardware Application Engineering Applicants are expected to have a solid experience in handling Job related tasks
Staff Firmware Engineer - high-speed interconnects /custom silicon/ASIC design / microcontroller architectures / Applicants are expected to have a solid experience in handling Job related tasks
Analog IC Design, Staff Engineer Applicants are expected to have a solid experience in handling Staff Engineer related tasks
Distinguished Engineer, Verification Applicants are expected to have a solid experience in handling Verification related tasks