Power Delivery Design Engineer job opportunity at Intel.

Home Jobs In India Tag: Job Power Delivery Design Engineer position at Intel


DatePosted 12 Days Ago bot
Intel Power Delivery Design Engineer
Experience: 15-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeBachelor's (B.A.)
loacation India, Bangalore, India
loacation India, Bangalo..........India

Job Details: Job Description:  Works on end-to-end power delivery design and development, spanning initial concept to implementation of power delivery requirements and ecosystem enabling of power integrated circuits. Designs power delivery solutions to meet energy efficiency and performance goals. Defines, implements, and analyzes power delivery networks including 2D and 3D model extraction and noise analysis to meet platform specifications. Applies knowledge of power conversion topologies including components, compensation circuits/stability analysis, drop/droop analysis, simulation tools, and techniques as well as PCB layout and design tools to characterize performance and validate correlation of simulation modeling and results. Designs and validates platform power conversion and management solutions including energy management and performs simulation and optimization for package and PCB including stack up, power/ground noise plane assignment, decoupling solutions and/or power sequencing requirements. Collaborates with silicon and platform architects in generating solutions and analysis in delivering content into platform design guide as solution collaterals to the end customer. Architects VR specifications, creates test bench, test plans, and RTL models for emulation. Validates and correlates VR test tools and VR behavioral models with hardware. Qualifications: Should possess a Bachelor of Engineering or a Master degree of Engineering in the field of Electronics or Power Electronics with 15+ years' experience in Electronics circuit design or hardware system board design related to VR design Power delivery and hardware Power management domains. Work experience with IMVP design is preferred. Tool knowledge required for board design Concept HDL for schematics capture, BOM tools and Cadence Allegro and Sigrity Power DC for PCB layout reviews. Tool knowledge required for board debug and validation High speed oscilloscopes, electronic loads, DMM logic analyzer, soldering station etc. Ability to lead or Architect PD for a program and work independently with strong verbal communication and presentation skills.            Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location:  India, Bangalore Additional Locations: Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Other Ai Matches

Customer Validation Enabling Engineer - Intern Applicants are expected to have a solid experience in handling Job related tasks
Memory Debug Engineer Applicants are expected to have a solid experience in handling Job related tasks
Analog Circuit Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
CPU Backend Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Packaging Module Equipment Development Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior SoC Logic Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Intel Foundry Customer Quality Engineer Applicants are expected to have a solid experience in handling Job related tasks
Layout Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Director, Software Engineering Applicants are expected to have a solid experience in handling Software Engineering related tasks
Logic Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Senior Software Performance Engineer Applicants are expected to have a solid experience in handling Job related tasks
Network Monitoring Security Engineer Applicants are expected to have a solid experience in handling Job related tasks
Software Enabling and Optimization Engineer Applicants are expected to have a solid experience in handling Job related tasks
Supply Chain GSCO CoE Process Automation Program Manager Applicants are expected to have a solid experience in handling Job related tasks
Graduate Talent (Pre-si System Validation) Applicants are expected to have a solid experience in handling Job related tasks
Compiler Engineer Applicants are expected to have a solid experience in handling Job related tasks
Mechanical\Materials\Chemical Engineering Student for Intel Kiryat Gat Applicants are expected to have a solid experience in handling Job related tasks
Platform Application Engineer (DPDK/Cloud-native/AI) Applicants are expected to have a solid experience in handling Job related tasks
Senior Account Sales Manager Applicants are expected to have a solid experience in handling Job related tasks
FCS Risk and Audit Manager Applicants are expected to have a solid experience in handling Job related tasks
SoC Design Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
Rebate Global Process Owner Analyst Applicants are expected to have a solid experience in handling Job related tasks
Graduate Talent [E-core (Atom) CPU Circuit Design] Applicants are expected to have a solid experience in handling Job related tasks