Clocking Design Engineer job opportunity at Intel.

Home Jobs In United States Of America Tag: Job Clocking Design Engineer position at Intel


DatePosted 30+ Days Ago bot
Intel Clocking Design Engineer
Experience: 4-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation US, Texas, Austin, United States Of America
loacation US, Texas, Aus..........United States Of America

Job Details: Job Description:  We are seeking a highly skilled Clocking Design Engineer to join our dynamic team. You will be part of the clock team supporting Intel’s flagship CPU designs in the most advanced process nodes. In this role, you will be involved in clocking architecture definition, design and implementation of custom clock global network, development of clock tree synthesis flow, as well as custom clock circuit design and clock library cell design. This is a cross-functional role that requires interfacing and collaborating with other teams such as architecture, physical design, full chip integration, RTL, circuits, validation, design automation team and EDA vendors, in a high-paced atmosphere. Key Responsibilities: Implement custom clock distribution network for high frequency flagship CPU designs Develop clock tree synthesis flow and deliver custom clock solutions for high frequency flagship CPU designs Design custom circuits and library cells related to clock distribution Qualifications: You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor´s degree in electrical engineering, computer engineering related STEM field and 4+ years of experience and/or Master´s degree and 3+ years of experience and/or PhD and 2+ years of experience, ​during which the candidate has demonstrated experience in: Physical design and advanced process technologies and circuit implementation Static timing analysis, clock tree synthesis, and clock-related timing parameters Use of industry-standard scripting and automation within EDA tool flows Preferred Qualifications: 3+ years of experience in: Backend design and/or integration on leading edge process nodes High frequency clock distribution design and implementation, custom circuits and clock tree synthesis             Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location:  US, Texas, Austin Additional Locations: US, Oregon, Hillsboro Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .     Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD     The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.     Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Other Ai Matches

Senior Electrical Validation Engineer Applicants are expected to have a solid experience in handling Job related tasks
Foundational IP Integration QA Lead Applicants are expected to have a solid experience in handling Job related tasks
APTD: SWA Integration On Shift (IOS) TD Engineer - Shift 5 Applicants are expected to have a solid experience in handling Job related tasks
Principal Logic Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Platform Power and Performance Manager Applicants are expected to have a solid experience in handling Job related tasks
Senior Program Manager Applicants are expected to have a solid experience in handling Job related tasks
Physical Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Software Engineering - Intern, Graduate Applicants are expected to have a solid experience in handling Graduate related tasks
Cost and Inventory Analyst Applicants are expected to have a solid experience in handling Job related tasks
CPU Formal Verification Engineer Applicants are expected to have a solid experience in handling Job related tasks
3D and AI Software Engineering Intern Applicants are expected to have a solid experience in handling Job related tasks
Staff PDK Development Engineer - PERC ESD Verification Applicants are expected to have a solid experience in handling Job related tasks
Process and Equipment Engineer (Contract) Applicants are expected to have a solid experience in handling Job related tasks
Graduate Talent (MPE DDG) Applicants are expected to have a solid experience in handling Job related tasks
Pre-Silicon Validation Engineer Applicants are expected to have a solid experience in handling Job related tasks
Intel Foundry Customer Quality Engineer Applicants are expected to have a solid experience in handling Job related tasks
Graduate Talent (MPE DDG) Applicants are expected to have a solid experience in handling Job related tasks
Senior Performance Architect Applicants are expected to have a solid experience in handling Job related tasks
AI/GPU SoC Lead Applicants are expected to have a solid experience in handling Job related tasks
Intel Foundry Senior Customer Quality Engineer Applicants are expected to have a solid experience in handling Job related tasks
Application Owner, DEAP Platform Applicants are expected to have a solid experience in handling DEAP Platform related tasks
NPI Integrator Applicants are expected to have a solid experience in handling Job related tasks
Middleware Software Engineering Intern Applicants are expected to have a solid experience in handling Job related tasks